Espressif Systems announced the ESP32-S31, a new dual-core RISC-V microcontroller featuring Wi-Fi 6 and Gigabit Ethernet connectivity [1, 2].
This release marks a significant shift for the ESP32 family by moving to an open-standard instruction set architecture. By integrating high-speed networking into a low-power device, the company targets a new tier of industrial and consumer IoT applications that require higher throughput than previous generations.
Announced in April 2026 [2], the chip is the first in the ESP32 series to utilize a dual-core RISC-V architecture [2]. The hardware is designed to modernize the company's microcontroller portfolio through the adoption of the 802.11ax Wi-Fi 6 standard [1].
Connectivity is a primary focus of the new hardware. The ESP32-S31 supports 1 Gbps Gigabit Ethernet [1], providing a substantial increase in wired data speeds for embedded systems. This combination of wireless and wired capabilities allows developers to build more resilient network nodes.
"The ESP32-S31 is the first ESP32 series to feature a dual-core RISC-V architecture," the Hackaday editorial team said [2].
Espressif, headquartered in Shanghai, China [1], developed the chip to bring modern architecture and faster connectivity to its existing product line. The company intends to maintain its focus on low-power consumption while increasing the processing ceiling for developers.
"We’re excited to bring Wi-Fi 6 and Gigabit Ethernet to our low-power MCU portfolio," an Espressif spokesperson said [1].
“The ESP32-S31 is the first ESP32 series to feature a dual-core RISC-V architecture.”
The transition to RISC-V suggests a strategic move toward open-source hardware standards, reducing reliance on proprietary architectures. By pairing this with Gigabit Ethernet and Wi-Fi 6, Espressif is positioning the ESP32-S31 to compete in high-bandwidth IoT environments, such as edge computing and industrial automation, where legacy low-power chips previously lacked sufficient throughput.
