d-Matrix Unveils Raptor AI Accelerator with 100 TB/s Bandwidth

AI chip startup d-Matrix has presented its Raptor accelerator, a 3D-stacked chip delivering roughly 100 TB/s of memory bandwidth per card ^[1].

The architecture targets the primary bottleneck of generative AI inference: the energy and speed required to move data between memory and the processor. By eliminating traditional memory layouts, the Raptor aims to reduce power consumption while increasing the density of data throughput.

Unveiled this week at the IEEE Hot Chips 2026 conference, the Raptor utilizes a specialized manufacturing process provided by TSMC [1, 2]. The design bonds a four nm compute die directly onto a custom-designed DRAM die ^[1]. This face-to-face bonding is achieved using a micro-bump pitch of 36 microns ^[1].

This structural change allows the chip to operate with higher efficiency than current industry standards. According to technical data, the Raptor uses approximately one-sixth the energy per bit compared to HBM3 solutions ^[3]. This energy reduction is critical for data centers managing massive large language models that require constant memory access.

Performance metrics indicate a substantial leap in bandwidth density. The Raptor offers a 20x bandwidth density advantage over the NVIDIA Rubin architecture ^[5]. This leap is attributed to the direct stacking of compute and memory, which shortens the physical distance data must travel.

By integrating the DRAM directly beneath the compute logic, d-Matrix intends to provide the necessary throughput for next-generation AI workloads without the proportional increase in heat and power typically associated with high-bandwidth memory. The company presented these findings to the hardware community during the conference to demonstrate a viable alternative to existing HBM-based accelerators [1, 3].