Huawei Technologies Co. Ltd. has introduced a new chip architecture called "τ-Scaling" to continue performance growth without relying solely on transistor miniaturization [1, 2].
The announcement marks a strategic pivot for the company as it seeks to maintain technological competitiveness while facing restrictive U.S. sanctions on its semiconductor supply chain [4, 5]. By optimizing the entire computing stack, Huawei intends to bypass the physical limits that have historically governed the semiconductor industry.
Presented at the International Solid-State Circuits Conference (ISSCC) 2026 in San Francisco, the framework shifts the focus from shrinking individual components to system-wide efficiency [3, 4]. The company describes the approach as a way to maintain the trajectory of computing power, a goal traditionally associated with Moore's Law, through a different architectural lens [2].
"τ-Scaling allows us to continue performance growth without relying solely on transistor scaling," He Tingbo, Senior Vice President at Huawei, said [2].
The company has set aggressive benchmarks for the new technology. A Huawei spokesperson said the firm aims to achieve chip performance equivalent to a 1.4nm process by 2031 [3]. This target represents a significant leap in density and efficiency, achieved through the τ-Scaling framework rather than traditional lithography [1].
While the long-term goal extends to 2031, the company is moving faster on its immediate roadmap. A spokesperson said Huawei will deliver industry-leading semiconductors using this new technology within the next five years [3, 5]. This timeline suggests a rollout of high-performance chips by 2031, though some internal targets for industry-leading hardware may be reached as early as 2031 [3].
The development is taking place within Huawei's research and development facilities in China [3, 4]. The move is widely viewed as a "sanctions-busting" effort to ensure the company can produce advanced AI and computing hardware despite limited access to the most advanced global fabrication tools [4, 5].
“"τ-Scaling allows us to continue performance growth without relying solely on transistor scaling."”
Huawei's shift toward τ-Scaling signals a move away from the industry's obsession with smaller nanometer nodes, which are heavily gated by U.S. export controls on extreme ultraviolet (EUV) lithography. By focusing on the 'computing stack'—software, interconnects, and architecture—Huawei is attempting to achieve the same performance gains as a 1.4nm chip using less advanced manufacturing processes. If successful, this would decouple high-performance computing from the need for the world's most advanced fabrication plants.
