Huawei Technologies Co. announced a new chip-design method on May 25, 2026 [4], that stacks multiple logic layers to increase processing power.
This development is a strategic attempt to circumvent U.S. export restrictions and the physical limitations of Moore’s Law. Because sanctions have forced Chinese fabrication plants to rely on older process nodes, Huawei is seeking architectural alternatives to maintain competitiveness in high-performance computing.
The company describes the method as "logic-folding," which involves stacking multiple layers of circuitry and connecting them using microscopic copper bonds. Huawei said this architecture can deliver a performance increase of up to 53% [1]. This approach allows the company to gain efficiency without needing the ultra-advanced lithography machines currently blocked by trade curbs.
Beyond immediate performance gains, the company is pursuing a long-term strategy known as the "Tau Scaling Law." This roadmap aims to achieve a transistor density equivalent to a 1.4 nm process by 2031 [2]. By focusing on vertical scaling rather than just shrinking transistors, Huawei hopes to sustain the growth of computing power over the next several years.
However, the practical application of this technology remains a point of contention. While the company promotes the folded-chip architecture, reports regarding its hardware are mixed. Some analysis of the new MateBook Fold laptop suggests the device is powered by an older-generation SMIC chip, indicating that the most advanced logic-folded designs may not yet be in mass production for consumer electronics.
Huawei has invested heavily in this pursuit for over two decades. The company allocated an annual budget of $400 million to its chip program as early as 2003 [3]. This long-term financial commitment underscores Beijing's broader goal of achieving semiconductor self-sufficiency in the face of ongoing geopolitical tensions.
“Huawei announced a new chip-design method... that stacks multiple logic layers to increase processing power.”
Huawei's shift toward 3D logic stacking represents a pivot from traditional semiconductor scaling to architectural innovation. By focusing on how chips are layered rather than just how small the transistors are, the company is attempting to neutralize the impact of U.S. restrictions on extreme ultraviolet (EUV) lithography. If successful, this could prove that architectural workarounds can sustain high-end computing growth even when the most advanced manufacturing hardware is unavailable.
